// $Module: reg_ive_ncc $
// $RegisterBank Version: V 1.0.00 $
// $Author: andy.tsao $
// $Date: Thu, 25 Nov 2021 03:58:50 PM $
//

//GEN REG ADDR/OFFSET/MASK
#define  IVE_NCC_REG_NCC_00  0x0
#define  IVE_NCC_REG_NCC_01  0x4
#define  IVE_NCC_REG_NCC_02  0x8
#define  IVE_NCC_REG_NCC_03  0xc
#define  IVE_NCC_REG_NCC_04  0x10
#define  IVE_NCC_REG_NCC_05  0x14
#define  IVE_NCC_REG_NCC_06  0x18
#define  IVE_NCC_REG_NCC_07  0x1c
#define  IVE_NCC_REG_NCC_08  0x20
#define  IVE_NCC_REG_NCC_09  0x24
#define  IVE_NCC_REG_NCC_10  0x28
#define  IVE_NCC_REG_NCC_11  0x2c
#define  IVE_NCC_REG_NUMERATOR_L   0x0
#define  IVE_NCC_REG_NUMERATOR_L_OFFSET 0
#define  IVE_NCC_REG_NUMERATOR_L_MASK   0xffffffff
#define  IVE_NCC_REG_NUMERATOR_L_BITS   0x20
#define  IVE_NCC_REG_NUMERATOR_H   0x4
#define  IVE_NCC_REG_NUMERATOR_H_OFFSET 0
#define  IVE_NCC_REG_NUMERATOR_H_MASK   0xff
#define  IVE_NCC_REG_NUMERATOR_H_BITS   0x8
#define  IVE_NCC_REG_QUADSUM0_L   0x8
#define  IVE_NCC_REG_QUADSUM0_L_OFFSET 0
#define  IVE_NCC_REG_QUADSUM0_L_MASK   0xffffffff
#define  IVE_NCC_REG_QUADSUM0_L_BITS   0x20
#define  IVE_NCC_REG_QUADSUM0_H   0xc
#define  IVE_NCC_REG_QUADSUM0_H_OFFSET 0
#define  IVE_NCC_REG_QUADSUM0_H_MASK   0xff
#define  IVE_NCC_REG_QUADSUM0_H_BITS   0x8
#define  IVE_NCC_REG_QUADSUM1_L   0x10
#define  IVE_NCC_REG_QUADSUM1_L_OFFSET 0
#define  IVE_NCC_REG_QUADSUM1_L_MASK   0xffffffff
#define  IVE_NCC_REG_QUADSUM1_L_BITS   0x20
#define  IVE_NCC_REG_QUADSUM1_H   0x14
#define  IVE_NCC_REG_QUADSUM1_H_OFFSET 0
#define  IVE_NCC_REG_QUADSUM1_H_MASK   0xff
#define  IVE_NCC_REG_QUADSUM1_H_BITS   0x8
#define  IVE_NCC_REG_CROP_ENABLE   0x18
#define  IVE_NCC_REG_CROP_ENABLE_OFFSET 0
#define  IVE_NCC_REG_CROP_ENABLE_MASK   0x1
#define  IVE_NCC_REG_CROP_ENABLE_BITS   0x1
#define  IVE_NCC_REG_CROP_START_X   0x1c
#define  IVE_NCC_REG_CROP_START_X_OFFSET 0
#define  IVE_NCC_REG_CROP_START_X_MASK   0xffff
#define  IVE_NCC_REG_CROP_START_X_BITS   0x10
#define  IVE_NCC_REG_CROP_START_Y   0x20
#define  IVE_NCC_REG_CROP_START_Y_OFFSET 0
#define  IVE_NCC_REG_CROP_START_Y_MASK   0xffff
#define  IVE_NCC_REG_CROP_START_Y_BITS   0x10
#define  IVE_NCC_REG_CROP_END_X   0x24
#define  IVE_NCC_REG_CROP_END_X_OFFSET 0
#define  IVE_NCC_REG_CROP_END_X_MASK   0xffff
#define  IVE_NCC_REG_CROP_END_X_BITS   0x10
#define  IVE_NCC_REG_CROP_END_Y   0x28
#define  IVE_NCC_REG_CROP_END_Y_OFFSET 0
#define  IVE_NCC_REG_CROP_END_Y_MASK   0xffff
#define  IVE_NCC_REG_CROP_END_Y_BITS   0x10
#define  IVE_NCC_REG_SHDW_SEL   0x2c
#define  IVE_NCC_REG_SHDW_SEL_OFFSET 0
#define  IVE_NCC_REG_SHDW_SEL_MASK   0x1
#define  IVE_NCC_REG_SHDW_SEL_BITS   0x1
